3.5: Optimization of LTPS‐AMOLED Array Design to Enhance the Resistance to ESD risk

• DOI: 10.1002/sdtp.13376
• Publication Date: 2019-10-04T09:10:47Z
• Authors: Yu Jin; Fei Hu; Jiali Ma; Nan Shen; Wangfeng Xi; Yunlei Lu; Haifeng Lu; Rulong Li
• Keywords: Jumper; Line (geometry)

Electrostatic discharge (ESD) is a significant cause of yield loss in FPD (Flat Panel Display) array manufacturing. LTPS‐TFT Arrays processing includes series chucking and conveyance steps, which, some these steps would generate triboelectric charge [1, 2]. Although low‐impedance materials for equipment contact parts with glass substrate have been adopted, good grounding has implemented, ESD still happens frequently. In order to understand the root‐cause minimize effect, it necessary systematic research on processing. By studying identifying locations different LTPS‐AMOLED products , we found three causes related designs as described below: Overlap between adjacent metal layers easy ESD, e.g. overlap 1 line EM 2 jumper Vdata, Vdata VDD, Vref Vdata. Research products’ GIP (Gate Driver Panel) area indicates that distance Capacity C1/C2 GIP‐Scan circuit, D1 short, difference an obvious correlation which resistance risk enhanced increase decrease C1/C1 difference. Study CT (Cell Test) shows strong IC Pad, including COF Pad & output occurs easily when connected circuit directly. optimizing design, excellent risks can be obtained.