Generation of surrogate models of Pareto-optimal performance trade-offs of planar inductors

0202 electrical engineering, electronic engineering, information engineering 02 engineering and technology
DOI: 10.1007/s10470-013-0230-8 Publication Date: 2013-11-27T06:12:45Z
ABSTRACT
Systematic design methodologies for wireless transceivers require an efficient design of integrated inductors. Early availability of feasible trade-offs between inductance, quality factor, self-resonance frequency and area, is a key enabler towards the improvement of such design methodologies. This paper introduces such an approach in two steps. First, a Pareto-optimal performance front of integrated inductors is generated by embedding a performance evaluator into a multi-objective optimization tool. Then, starting from the optimal front samples, a surrogate model of the performance front is obtained. Experimental results in a 0.35-μm CMOS technology are provided.
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