Design and First Tests From Room Temperature to 200 mK of a 16-to-1 CMOS Multiplexing ASIC for High Impedance NbSi TESs

• DOI: 10.1007/s10909-024-03236-5
• Publication Date: 2024-11-13T08:02:44Z
• Authors: Benjamin Criton; Xavier de la Broïse; Jean-Luc Sauvageot
• Keywords: Application-specific integrated circuit; Focused Impedance Measurement

Abstract Achieving high spectral and spatial resolution of wide astrophysical objects in the X-ray band will be main focus future space telescopes. We explore a new technological solution based on impedance NbSi TES detectors ( $$\sim $$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mo>∼</mml:mo> </mml:math> 2 M $$\Omega <mml:mi>Ω</mml:mi> ) enabling transfer pre-amplification stage to higher temperatures (4 K) use 50 mK CMOS time-division multiplexer reduce power dissipation at mK. present design first tests, down 200 mK, this ASIC eventually able work multiplexing 16 one 4 K amplifier with total budget under $$\mu <mml:mi>μ</mml:mi> W. In parallel development we fabricated 4-by-4 pixel matrices build complete demonstrator (comprising detector array, presented another paper published, amplification stage). aim frame time 48 s leaving 3 for reading-out each pixel. The embeds parasitic capacity compensation techniques.