A Novel FPGA Architecture of a 2-D Wavelet Transform

• DOI: 10.1007/s11265-006-4188-y
• Publication Date: 2006-02-14T05:32:43Z
• Authors: Ricardo José Colo...; Rafael Gadea Gironés; Angel Sebastia Co...
• Keywords: Clock rate

This paper presents a new architecture for implementing a two-dimensional Discrete Wavelet Transform (2-D DWT). This architecture works in a non-separable fashion using a parallel filter structure with distributed control to compute all the DWT resolution levels. The architecture is modular and scalable in its totality. In this way, the input sample can be processed at the rate of one sample per clock cycle. To compute an N × N still image with a filter length L, N2?+?N clock cycles and 4.5N memory storage cells are required. Implementation results based on a Xilinx Virtex FPGA device are included.