Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System

• DOI: 10.1007/s11265-020-01558-7
• Publication Date: 2020-07-09T08:08:43Z
• Authors: Andreas Grübl; Sebastian Billaud...; Benjamin Cramer; Vitali Karasenko; Johannes Schemmel
• Keywords: Neuromorphic engineering; Application-specific integrated circuit; SIMD

Abstract This paper presents verification and implementation methods that have been developed for the design of BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits two general purpose microprocessors (PPU) SIMD extension on-chip learning plasticity. Simulation automated analysis pre-tapeout calibration highly parameterizable neuron synapse hardware-software co-development digital logic software stack presented. Accelerated operation highly-parallel data buses part PPU require custom methodologies to close signal timing at interfaces. Novel extensions standard physical flow highlighted. We present early results from first full-size ASIC containing 512 neurons 130 K synapses, demonstrating successful application these methods. An example illustrates full functionality hybrid plasticity architecture.