Analysis and optimization of dynamically reconfigurable regenerative comparators for ultra-low power 6-bit TC-ADCs in 90 nm CMOS technologies

• DOI: 10.1016/j.mejo.2014.02.005
• Publication Date: 2014-03-01T03:45:38Z
• Authors: Juan A. Montiel-N...; Víctor Navarro; Javier Sosa; Tomás Bautista
• Keywords: Linearity

In this paper, the optimization and analysis of threshold configurable regenerative comparators (TC) for use in ultra-low power consumption ADCs is introduced (TC-ADC). Using a 90 nm CMOS technology, obtained comparator achieves 77% improvement terms (3μW) when compared with previously published TC comparators, while maintains same full scale specification (±160 mv). The proposed design exhibits delay time 1.31 ns — 20% which allows achieving 6-bit TC-ADC up to 25 MS/s sampling period 40 ns. Furthermore, offset, gain non-linearity errors also analyzed both perfectly matched devices under presence manufacturing dependent device mismatch scenarios. higher energy efficiency optimized increases linearity by 50% gain, DNL INL. Although, 30 MonteCarlo simulations 3σ parameter variations offset one are diminished 37%, 12% 17%, respectively.