A low-noise, 0.05–17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators

• DOI: 10.1016/j.mejo.2024.106140
• Publication Date: 2024-02-29T19:38:26Z
• Authors: Depeng Sun; Ruiqing Wang; Feng Bu; Yuan Gao; Xiaoteng Zhao; Ruixue Ding; Shubin Liu; Rong Zhou
• Keywords: dBc; Wideband

This paper presents a low-noise ultra-wideband fractional-N change pump phase-locked loop (CPPLL). By adopting two parallel voltage-controlled oscillators (VCOs) and the synchronized dual-core design, 8.5–17.8-GHz output is covered phase noise reduced by about 3 dB with halving total equivalent inductance of tank. Meanwhile, clock distribution designed to obtain 0.05–8.9-GHz output. using retiming separate division techniques, frequency coupling solved, implementation separated from its considerations, which alleviates design complexity. Fabricated in 65-nm CMOS process, proposed CPPLL verified, it achieves −109.9-dBc/Hz@1 MHz −71.6-dBc reference spur at 16-GHz The integrated jitter 144 fs 10 kHz 100 MHz.