Count overflow and privilege mode filtering extension implementation on a RISC-V on-board processor

• DOI: 10.1016/j.micpro.2024.105084
• Publication Date: 2024-07-14T08:05:26Z
• Authors: Andrea Fernández ...; Miguel Jiménez Ar...; Iván Gamino del Río; Agustín Martínez ...; Manuel Prieto Mateo; Óscar Rodríguez Polo; Antonio da Silva; Pablo Parra; Sebastián Sánchez
• Keywords: Microarchitecture; Processor design

RISC-V is a computer architecture that has recently attracted considerable attention due to its advantageous qualities: it an open instruction set, based on reduced and simple instructions. For this reason become appealing choice for wide range of computing applications positioned as disruptive force in variety fields, including those involve the development safety–critical software, space sector. The ability evaluate activities performed within processor paramount importance type systems ensure fulfillment requirements during missions. monitoring these events inside managed by instrument called Hardware Performance Monitor (HPM). This work shows implementation Sscofpmf extension HPM compliant privileged specification. paper details redesign existing performance counters from baseline version previously implemented. A comparison between two versions both resource utilization data power consumption also provided. As expected, higher utilization. Nevertheless, additional functionalities included system have been validated without any changes clock frequency, so does not introduce overhead.