Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions

• DOI: 10.1016/j.microrel.2018.07.018
• Publication Date: 2018-09-30T08:13:45Z
• Authors: Y.Q. Aguiar; F. Wrobel; J.-L. Autran; P. Leroux; F. Saigné; A.D. Touboul; V. Pouget
• Keywords: 0103 physical sciences; 01 natural sciences; [SPI.TRON]Engineering Sciences [physics]/Electronics

Abstract For nanometer technologies, SET is increasingly growing in importance in circuit design. Accordingly, different hardening techniques were developed to reduce the Soft-Error Rate. Considering selective node hardening technique based on standard cells, this work evaluates the SET response of logic gates from a Standard-Cell library under heavy ions. Overall, it is observed that the usage of NOR and NAND gates coupled with an output inverter provides reduced SET cross-section and increased threshold LET compared with the standalone OR gate and AND gate, respectively. With the results gathered in this work, circuit designers can implement reliability-aware synthesis algorithms with selective hardening more efficiently to tackle the threat of SET in combinational circuits.