FPGA-based signal processing for the LHCb silicon strip detectors

• DOI: 10.1016/j.nima.2006.09.079
• Publication Date: 2006-11-10T07:27:55Z
• Authors: G. Haefeli; A. Bay; A. Gong
• Keywords: Gigabit Ethernet; Disk formatting; Gigabit; STRIPS; Interface (matter)

Abstract We have developed an electronic board (TELL1) to interface the DAQ system of the LHCb experiment at CERN. Two hundred and eighty-nine TELL1 boards are needed to read out the different subdetectors including the silicon VEertex LOcator (VELO) (172 k strips), the Trigger Tracker (TT) (147 k strips) and the Inner Tracker (129 k strips). Each board can handle either 64 analog or 24 digital optical links. The TELL1 mother board provides common mode correction, zero suppression, data formatting, and a large network interface buffer. To satisfy the different requirements we have adopted a flexible FPGA design and made use of mezzanine cards. Mezzanines are used for data input from digital optical and analog copper links as well as for the Gigabit Ethernet interface to DAQ.