Radiation hardness of silicon-on-insulator pixel devices

• DOI: 10.1016/j.nima.2018.05.077
• Publication Date: 2018-06-14T08:43:50Z
• Authors: Kazuhiko Hara; Wataru Aoyagi; Daisuke Sekigawa; Shikie Iwanami; Shunsuke Honda; Toru Tsuboyama; Yasuo Arai; Ikuo Kurachi; Toshinobu Miyoshi; Miho Yamada; Yoichi Ikegami
• Keywords: Radiation hardening

Abstract Silicon-on-Insulator (SOI) CMOS is an attractive technology because of pixel sensor applications for its inherent advantages such as superior isolation of each FET by the surrounding insulator. We have been developing SOI pixel devices since 2005 using the FD-SOI technology and noticed that the insulator layers impose significant sensitivity to the total ionization dose (TID) effect. Research activities in the last ten years to improve radiation hardness are reviewed, such as introduction of buried wells and double SOI wafers.