JICG CMOS transistors for reduction of total ionizing dose and single event effects in a 130 nm bulk SiGe BiCMOS technology

• DOI: 10.1016/j.nima.2020.164832
• Publication Date: 2020-11-02T05:52:17Z
• Authors: R. Sorge; J. Schmidt; Ch. Wipf; F. Reimer; F. Teply; F. Korndörfer
• Keywords: Shallow trench isolation; Leakage (economics); BiCMOS

We report on a novel radiation hardening by design (RHBD) approach for mitigation of total ionization dose (TID) induced drain leakage currents and single event transient (SET) in digital circuits fabricated 130 nm bulk SiGe BiCMOS technology. In order to avoid significant TID increase NMOS transistors channel pinch-off PMOS due positive charges trapped at the lateral shallow trench insulator silicon interface we introduced junction isolation (JI) MOS regions. The device construction measures applied also support suppress generation SETs. tolerance JI against was verified up > 1.3 Mrad(Si). SET tests performed four different inverter types varying arrangement deep well layout. For CMOS inverters with isolated LET threshold MeV cm2 mg−1 obtained.