Emerging silicon-on-nothing (SON) devices technology

• DOI: 10.1016/j.sse.2003.12.013
• Publication Date: 2004-02-05T10:35:33Z
• Authors: S. Monfray; T. Skotnicki; C. Fenouillet-Ber...; N. Carriere; D. Chanemougame; Y. Morand; S. Descombes; A. Talbot; D. Dutartre; C. Jenny; P. Mazoyer; R. Palla; F. Leverd; Y. Le Friec; R. Pantel; S. Borel; D. Louis; N. Buffet
• Keywords: 02 engineering and technology; 0210 nano-technology

Abstract In this paper we explain the advantages of very thin layers (in the channel and in the BOX) of the silicon-on-nothing (SON) transistors. Electrical results are also presented, with gate length down to 38 nm, with a conduction channel thickness as thin as 9 and 5 nm. It is also demonstrated that SON is better suited than bulk for accepting a metallic gate for low-voltage operation due to its intrinsic low threshold voltage. We have integrated midgap CoSi 2 metal gate by total gate silicidation on SON transistors with Si-conduction channel thickness down to 5 nm. Finally, we will analyse the ITRS’01 CMOS Roadmap and show that SON allows reaching the I on / I off specifications down to the 32 nm node and approaching closely those for the 22 nm node, that is by far impossible with bulk.