Junctionless Nanowire Transistor (JNT): Properties and design guidelines

• DOI: 10.1016/j.sse.2011.06.004
• Publication Date: 2011-07-29T05:22:54Z
• Authors: J.P. Colinge; A. Kranti; R. Yan; C.W. Lee; I. Ferain; R. Yu; N. Dehdashti Akhavan; P. Razavi
• Keywords: 02 engineering and technology; 0210 nano-technology

Conduction mechanisms in junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon.