Grain size engineering via a Hf0.5Zr0.5O2 seed layer for FeFET memory and synaptic devices

• DOI: 10.1039/d4nr05381h
• Publication Date: 2025-03-14T08:41:20Z
• Authors: Junhyeok Park; Chulwon Chung; Boncheol Ku; Seunghyeon Yun; Kyungsoo Park; Changhwan Choi

A ferroelectric thin film using a seed layer and a higher deposition temperature process brings about a reduction in grain size, leading to lower device-to-device variation and improved electrical characteristics including P–V and synaptic functions.