FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks

• DOI: 10.1109/a-sscc53895.2021.9634714
• Publication Date: 2021-12-10T20:45:05Z
• Authors: Changhyeon Kim; Dongyoung Rim; Jeongwon Choe; Dongyun Kam; Giyoon Park; Seokki Kim; Youngjoo Lee
• Keywords: BCH code; Block Error Rate

The ordered statistic decoding (OSD) approach for short-length BCH codes has been continuously considered as one of the promising error-correction by achieving a block error rate (BLER) less than $10^{-6}$, which is attractive to ultra-reliable and low-latency communication (URLLC) industrial IoT (IIOT) solutions [1], [2]. However, it hard directly realize conventional OSD algorithm because compute-intensive Gaussian elimination iterative reprocessing steps. Based on recent segmentation discarding (SDD) [3], in this work, we newly present an ultralow-latency architecture reducing latency 12 times, implemented at FPGA-based verification platform.