A Delay Metric for VLSI Interconnect

• DOI: 10.1109/icasic.2005.1611479
• Publication Date: 2006-04-06T20:21:22Z
• Authors: Du Zhong; Wen Zhiping; Yu lixin
• Keywords: 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology

The Elmore delay RC metric, used widely to analysis interconnect delay, becomes ineffective for deep submicron technologies. Many interconnect delay models have been proposed by analyzing the moments of the impulse response, which are either computationally expensive or less accurate. In this paper, we present a new delay metric based on the first three moments of the impulse response, which has simple closed form expression and fast computation speed. The new metric is theoretically proven to be strictly less than the Elmore metric and is aprovably stable approximation. In the test for industrial nets, the average error is 3.8% for our model, less than other metrics