A 32-Gb/s C2C-DAC-Based PAM-4 Wireline Transmitter With Two-Tap Feed-Forward Equalization and Level-Mismatch Correction in 28-nm CMOS

• DOI: 10.1109/lmwc.2018.2870931
• Publication Date: 2018-09-28T20:50:45Z
• Authors: Boyu Hu; Yanghyo Kim; Rulin Huang; Yuan Du; Mau-Chung Frank C...
• Keywords: Wireline

This letter presents a C2C-DAC-based PAM-4 wireline transmitter that utilizes capacitor-weighting within predriver stage for multitap multilevel signal summation in charge domain at the front end. Such unique approach isolates summing node from output to alleviate bandwidth limitation and also inherently provides passive voltage-scaling level-shifting without sacrificing its speed. A level-mismatch-correction scheme is adopted effectively enhance signaling quality. Implemented 28-nm CMOS, designed prototype achieves peak data rate of 32 Gb/s an energy efficiency 2.1 mW/Gb/s.