An architecture for 32-bit energy-efficient wallace tree carry save adder

• DOI: 10.1109/tel-net.2017.8343529
• Publication Date: 2018-04-23T23:44:33Z
• Authors: Madhu; Jai Gopal Pandey; Gaurav Dhiman
• Keywords: Carry (investment); Bit (key); Tree (set theory)

In this paper, a hybrid 1-bit full adder design is reported. The first implemented for 1 bit and further it has been utilize to 32-bit adder. circuit using Tanner EDA tools in 45-nm technology. Power delay performance parameters are compared with an existing of CMOS comparison the design, present implementation found offer substantial improvements area power speed. This work also proposes energy-efficient Wallace tree carry save on 45 nm based Compared adders, proposed offers shorter delay, consumes lesser dissipation, which makes more cost-efficient suitable real-time applications.