A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication

• DOI: 10.1109/tvlsi.2022.3166355
• Publication Date: 2022-04-22T19:36:00Z
• Authors: Yang Su; Bai-Long Yang; Chen Yang; Ze-Peng Yang; Yi-Wei Liu
• Keywords: Homomorphic Encryption; Multi-core processor

The ring learning with error (RLWE)-based fully homomorphic encryption (FHE) scheme has become one of the most promising FHE schemes. However, its performance is limited by multiplication, especially polynomial multiplication which occupies major computing resources. Therefore, efficient implementation crucial for high-performance applications. In this article, we present an area-efficient and highly unified reconfigurable multicore number theoretic transform (NTT)/inverse NTT (INTT) architecture (named MCNA), employs INTT multiplier a variable processing elements. To reduce latency, MCNA merges preprocessing postprocessing into constant-geometry INTT, respectively. Also, modular based on digital signal processor (DSP) proposed to speed up multiplication. order avoid designing independent memory access pattern read/write structure NTT/INTT presented. Furthermore, novel named "cyclic-sharing" 25% capacity. evaluated Xilinx Virtex-7 field-programmable gate array (FPGA) platform. Running at 250-MHz clock frequency, throughput achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.78\times \sim 9.32\times $ </tex-math></inline-formula> improvements in comparison prior works, while area efficiency lookup table (LUT) flip-flop (FF) improved notation="LaTeX">$1.25\times 4.79\times . For notation="LaTeX">$3.73\times 7.69\times enhancements, as well notation="LaTeX">$1.13\times 14.8\times improvements.