A 100 nm copper/low-k bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications

• DOI: 10.1109/vlsit.2002.1015370
• Publication Date: 2003-06-25T21:52:33Z
• Authors: G.C.-F. Yeap; J. Chen; P. Grudowski; Y. Jeon; Y. Shiho; W. Qi; S. Jallepalli; N. Ramani; K. Hellig; L. Vishnubhotla; T. Luo; H. Tseng; Y. Du; S. Lim; P. Abramowitz; C. Reddy; S. Parihar; R. Singh; M. Wright; K. Patterson; N. Benavides; D. Bonser; T.V. Gompel; J. Conner; J.J. Lee; M. Rendon; D. Hall; A. Nghiem; R. Stout; K. Weidemann; A. Duvallet; J. Alvis; D. Dyer; D. Burnett; P. Ingersoll; K. Wimmer; S. Veeraraghavan; M. Foisy; M. Hall; J. Pellerin; D. Wristers; M. Woo; C. Lage
• Keywords: 0103 physical sciences; 01 natural sciences

We report a 100 nm modular bulk CMOS technology platform with multi Vt and multi gate oxide integrated transistors that enables device and circuit co-design (M. Fukuma et al., VLSI Tech., 2000) techniques (e.g. well biasing and power down/reduction) for low standby power (LSP), high performance (HP), high speed (HS), and RF/analog system on chip (SoC) applications. The transistor performances are comparable to or better than recently reported data at the 100 nm technology node. This technology also features an all-layer copper/low-k (<3.0) interlayer dielectric (ILD) backend for speed improvement and dynamic power reduction (S. Parihar et al., Proc. IEDM, 2001).