Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration

• DOI: 10.1145/1142155.1142159
• Publication Date: 2006-07-25T14:14:26Z
• Authors: Zuoyuan Li; Xianlong Hong; Qiang Zhou; Jinian Bian; Hannah H. Yang; Vijay Pitchumani
• Keywords: 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology

New three-dimensional (3D) floorplanning and thermal via planning algorithms are proposed for thermal optimization in two-stacked die integration. Our contributions include (1) a two-stage design flow for 3D floorplanning, which scales down the enlarged solution space due to multidevice layer structure; (2) an efficient thermal-driven 3D floorplanning algorithm with power distribution constraints; (3) a thermal via planning algorithm considering congestion minimization. Experiments results show that our approach is nine times faster with better solution quality compared to a recent published result. In addition, the thermal via planning approach is proven to be very efficient to eliminate localized hot spots directly.