FaCSim

• DOI: 10.1145/1375657.1375670
• Publication Date: 2008-06-17T09:49:02Z
• Authors: Jaejin Lee; Junghyun Kim; Choonki Jang; Seungkyun Kim; Bernhard Egger; Kwangsub Kim; SangYong Han
• Keywords: Benchmark (surveying); Microarchitecture; Multi-core processor

There have been strong demands for a fast and cycle-accurate virtual platforms in the embedded systems area where developers can do meaningful software development including performance debugging context of entire platform. In this paper, we describe design implementation architecture simulator called FaCSim as first step towards such FacSim accurately models ARM9E-S processor core ARM926EJ-S processor's memory subsystem. It simulates exceptions interrupts to enable whole-system simulation OS. Since it is implemented modular manner C++, be easily extended with other system components by subclassing or adding new classes. based on an interpretive technique provide flexibility, yet achieving high speed. enables means three mechanisms. First, computes elapsed cycles each pipeline stage chunk incrementally adds up advance clock instead performing cycle-by-cycle simulation. Second, uses basic-block cache that caches decoded instructions at level. Finally, parallelized exploit multicore are available everywhere these days. Using 21 applications from EEMBC benchmark suite, FaCSim's accuracy validated against board ARM, accurate ±7% error margin. Due level caching parallelization, is, average, more than times faster ARMulator six SimpleScalar.