The ReNoC Reconfigurable Network-on-Chip

• DOI: 10.1145/2043662.2043669
• Publication Date: 2011-11-30T13:58:46Z
• Authors: Matthias Bo Stuart; Mikkel Bystrup St...; Jens Sparsø
• Keywords: Synthesis; Mapping; Performance; 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology; Configuration; Experimentation; Algorithms; Network-on-chip; System-on-chip; Routing

This article presents a reconfigurable network-on-chip architecture called ReNoC, which is intended for use in general-purpose multiprocessor system-on-chip platforms, and enables application-specific logical NoC topologies to be configured, thus providing both efficiency flexibility. The three novel algorithms that synthesize an topology, map it onto the physical ReNoC architecture, create deadlock-free, routing algorithms. We apply our mixture of real synthetic applications target different architectures. Compared conventional NoC, reduces power consumption by up 58% on average.