ParTejas

• DOI: 10.1145/3077582
• Publication Date: 2017-08-02T19:36:12Z
• Authors: Geetika Malhotra; Rajshekar Kalayappan; Seep Goel; Pooja Aggarwal; Abhishek Sagar; Smruti R. Sarangi
• Keywords: Speedup; POSIX Threads; Speculative multithreading; Speculative execution; Parsec

In this article, we present the design of a novel parallel architecture simulator called ParTejas . is timing simulation engine that gets its execution traces from instrumented binaries using fast shared-memory-based mechanism. Subsequently, waiting threads simulate multiple pipelines and an elaborate memory system with support for multilevel coherent caches. written in Java primarily derives speedups use data structures. Specifically, it uses lock-free slot schedulers to entity port effectively models contention at shared resources CPU system. Parallel ports remove need fine-grained synchronization allow each thread local clock. Unlike conventional simulators barriers epoch boundaries, sophisticated type barrier, known as phaser. A phaser allows perform additional work without other arrive barrier. Additionally, host Java-specific optimizations profiling schedule threads. With all our optimizations, demonstrate speedup 11.8× multi-issue in-order pipeline 10.9× out-of-order 64 threads, suite seven Splash2 Parsec benchmarks. The error limited 2% 4% compared strictly sequential