Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design

• DOI: 10.1145/3325066
• Publication Date: 2019-05-30T12:41:00Z
• Authors: Naixing Wang; Irith Pomeranz; Sudhakar M. Reddy; Arani Sinha; Srikanth Venkatar...
• Keywords: Benchmark (surveying); Guideline; Standard cell; Integrated circuit design; Integrated circuit layout

Design-for-manufacturability (DFM) guidelines are recommended layout design practices intended to capture features that difficult manufacture correctly. Avoiding such prevents the occurrence of potential systematic defects. Layout result in DFM guideline violations may not be avoided completely due constraints chip area, performance, and power consumption. A framework for translating into defects, faults, was described earlier. In a cell-based design, translated faults internal or external cells. this article, we focus on undetectable Using resynthesis procedure makes fine changes while maintaining constraints, target areas where large numbers related undetectable. By eliminating corresponding violations, ensure circuit does suffer from low-coverage detectable defects escaping detection, but failing field. The is applied benchmark circuits logic blocks OpenSPARC T1 microprocessor. Experimental results indicate improvement coverage significant.