An Instruction Inflation Analyzing Framework for Dynamic Binary Translators

• DOI: 10.1145/3640813
• Publication Date: 2024-01-15T11:27:12Z
• Authors: Benyi Xie; Yue Yan; Chenghao Yan; Sicheng Tao; Zhuangzhuang Zhang; Xinyu Li; Yanzhi Lan; Xiang Wu; Tianyi Liu; Tingting Zhang; Fuxin Zhang
• Keywords: Code (set theory); Binary translation; Spec#

Dynamic binary translators (DBTs) are widely used to migrate applications between different instruction set architectures (ISAs). Despite extensive research improve DBT performance, noticeable overhead remains, preventing near-native especially when translating from complex computer (CISC) reduced (RISC). For computational workloads, the main stems translated code quality. Experimental data show that state-of-the-art products have dynamic inflation of at least 1.46. This indicates on average, more than 1.46 host instructions needed emulate one guest instruction. Worse, closely correlates with However, detailed sources remain unclear. To understand inflation, we present Deflater , an analysis framework comprising a mathematical model, collection black-box unit tests called BenchMIAOes and trace-based simulator InflatSim . The model calculates overall based individual translation block optimizations. extract parameters DBTs without accessing source code. implements uses extracted simulate given DBT’s behavior. is valuable tool guide improvement. Using Deflater, simulated for three CISC-to-RISC DBTs: ExaGear, Rosetta2, LATX, errors 5.63%, 5.15%, 3.44%, respectively SPEC CPU 2017, gaining insights into these commercial DBTs. also efficiently models open QEMU suggests optimizations can substantially reduce inflation. Implementing suggested confirms Deflater’s effective guidance, 4.65% error, gains 5.47x performance