FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs

• DOI: 10.1145/3653458
• Publication Date: 2024-03-20T12:09:01Z
• Authors: Linfeng Du; Tingyuan Liang; Xiaofeng Zhou; Jinming Ge; Shangkun Li; Sharad Sinha; Jieru Zhao; Zhiyao Xie; Wei Zhang
• Keywords: Floor plan; High-Level Synthesis; Directive

Multi-die FPGAs are widely adopted for large-scale accelerators, but optimizing high-level synthesis designs on these faces two challenges. First, the delay caused by die-crossing nets creates an NP-hard floorplanning problem. Second, traditional directive optimization cannot consider resource constraints each die or timing issue incurred die-crossings. Furthermore, high algorithmic complexity and large scale lead to extended runtime legalizing floorplan of HLS under different configurations. To co-optimize directives multi-die FPGAs, we formulate co-search based bin-packing variants present iterative flows. The first (FADO 1.0) relies a pre-built QoR library. It involves greedy, latency-bottleneck-guided search, incremental legalization. Compared with global solution, it takes 693X~4925X shorter search time achieves 1.16X~8.78X better design performance, measured in workload execution time. remove time-consuming library generation, second flow 2.0) integrates analytical model redesigns accelerate convergence. Through experiments mixed dataflow non-dataflow designs, compared 1.0, FADO 2.0 further yields 1.40X performance average after implementation Alveo U250 FPGA.