A low-power high-speed true single phase clock divide-by-2/3 prescaler

• DOI: 10.1587/elex.10.20120913
• Publication Date: 2013-01-29T01:04:34Z
• Authors: Jianhui Wu; Zixuan Wang; Xincun Ji; Cheng Huang
• Keywords: 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology

A novel low power high-speed true single-phase clock-based (TSPC) divide-by-2/3 prescaler is presented. By modifying the precharge branch in TSPC flip-flop instead of AND gate conventional topologies, inverter between two flip-flops eliminated, and number switching stages reduced to 6. The designed SMIC 0.18µm CMOS process, simulating results show that maximum operating frequency divide-by-3 mode reaches 10GHz with 1.836mW consumption, 50% faster than circuit. divide-by-2 8GHz 1.34mW consumption.