Snake: An asynchronous pipeline for ultra-low-power applications

• DOI: 10.1587/elex.16.20190293
• Publication Date: 2019-06-03T22:04:41Z
• Authors: Zhi-jiu Zhu; Yi Yu; Xu Bai; Shu-shan Qiao; Yong Hei
• Keywords: Design flow; Dynamic voltage scaling; Asynchronous circuit

Voltage scaling is an effective technique for ultra-low-power applications. However, PVT variation degrades the robust of traditional synchronous pipelines severely when voltage scales into sub-threshold region. In this paper, we propose a register-based bundled-data asynchronous pipeline that can operate robustly in sub-threshold, called Snake. By looping match delay line, Snake halves design overhead compared to other pipelines. We also practical methodology which compatible with commercial EDA and needs only few modifications flow. Monte-Carlo SPICE simulation shows pipelined multiplier applying proposed techniques operates stably 0.2 V achieves minimum power 1.3 nW V, energy 1.07 pJ per cycle 0.3 V. It provides 6.7 times superiority over baseline 22% area overhead. Comparison works state art are quite competitive.