A 2.6 e-rms Low-Random-Noise, 116.2 mW Low-Power 2-Mp Global Shutter CMOS Image Sensor with Pixel-Level ADC and In-Pixel Memory

• DOI: 10.23919/vlsicircuits52068.2021.9492357
• Publication Date: 2021-07-28T20:33:42Z
• Authors: Min-Woong Seo; Myunglae Chu; Hyun-Yong Jung; Suksan Kim; Jiyoun Song; Junan Lee; Sung-Yong Kim; Jongyeon Lee; Sung-Jae Byun; Daehee Bae; Minkyung Kim; Gwi-Deok Lee; Heesung Shim; Changyong Um; Changhwa Kim; In-Gyu Baek; Doowon Kwon; Hongki Kim; Hyuksoon Choi; Jonghyun Go; JungChak Ahn; Jaekyu Lee; Changrok Moon; Kyupil Lee; Hyoung-Sub Kim
• Keywords: 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology

This paper presents a low-random noise of 2.6 e-rms, a low-power of 116.2 mW at video rate, and a high-speed up to 960 fps 2-mega pixels global-shutter type CMOS image sensor (CIS) using an advanced DRAM technology. To achieve a high performance global-shutter CIS, we proposed a novel architecture for the digital pixel sensor which is a remarkable global-shutter operation CIS with a pixel-wise ADC and an in-pixel digital memory. Each pixel has two small-pitch Cu-to-Cu interconnectors for the wafer-level stacking, and the pitch of each unit pixel is less than 5 μm which is the world’s smallest pixel embedding both pixel-level ADC and 22-bit memories.