A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory

• DOI: 10.23919/vlsicircuits52068.2021.9492476
• Publication Date: 2021-07-28T20:33:42Z
• Authors: Juhyoung Lee; Jihoon Kim; Wooyoung Jo; Sangyeob Kim; Sangjin Kim; Jinsu Lee; Hoi-Jun Yoo
• Keywords: Exponent

An energy-efficient floating-point DNN training processor is proposed with heterogenous bfloat16 computing architecture using exponent computing-in-memory (CIM) and mantissa processing engine. Mantissa free calculation enables pipelining of operation for while reducing MAC power by 14.4 %. 6T SRAM bitline charge reusing reduces memory access 46.4 The fabricated in 28 nm CMOS technology occupies 1.62×3.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area. It achieves 13.7 TFLOPS/W energy efficiency which 274× higher than the previous CIM processor.