Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications

• DOI: 10.23919/vlsit.2017.7998202
• Publication Date: 2017-08-09T16:18:06Z
• Authors: Daewon Ha; C. Yang; J. Lee; S. Lee; S. H. Lee; K.-I. Seo; H. S. Oh; E. C. Hwang; S. W. Do; S. C. Park; M.-C. Sun; D. H. Kim; J. H. Lee; M. I. Kang; S.-S. Ha; D. Y. Choi; H. Jun; H. J. Shin; Y. J. Kim; J. Lee; C. W. Moon; Y. W. Cho; S. H. Park; Y. Son; J. Y. Park; B. C. Lee; C. Kim; Y. M. Oh; J. S. Park; S. S. Kim; M. C. Kim; K. H. Hwang; S. W. Nam; S. Maeda; D.-W. Kim; J.-H. Lee; M. S. Liang; E. S. Jung
• Keywords: Extreme Ultraviolet Lithography

7nm CMOS FinFET technology featuring EUV lithography, 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> gen. dual Fin and 2 xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm [1]. fully applied to MOL contacts minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity smaller CD variation. A <inf xmlns:xlink="http://www.w3.org/1999/xlink">VT</inf> of 6T HD SRAM cell are 1.29 for PD (PG) 1.34 PU, respectively.