Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node

• DOI: 10.23919/vlsitechnologyandcir57934.2023.10185211
• Publication Date: 2023-07-24T13:36:33Z
• Authors: G. Sisto; R. Preston; R. Chen; G. Mirabelli; A. Farokhnejad; Y. Zhou; I. Ciofi; A. Jourdain; A. Veloso; M. Stucchi; O. Zografos; P. Weckx; G. Hellings; J. Ryckaert
• Keywords: Power network design; Limiting; Benchmark (surveying)

This paper evaluates the impact of backside power delivery on physical implementation a commercial 64-bit high-performance block from ARM™ at A14 node. A BEOL, including TSV connections, is proposed and calibrated using TCAD experimental data. The developed stack modeled in cell-level parasitic extraction tool to enable its use during place route. same benchmark physically implemented imec's own PDK. PDN enables frequency improvements 2% 6% compared frontside PDN, stemming core area reduction 8% 16%. These results are obtained without negatively impacting total simultaneously limiting dynamic IR drop below 35mV. Furthermore, different options have been studied potentially boost gains up 23%.