Design and Simulation of Single Electron Transistor based SRAM and its Memory Controller at Room Temperature

• DOI: 10.30880/ijie.2019.11.06.020
• Publication Date: 2019-10-19T23:12:37Z
• Authors: Jignesh Badgujar; Vishwamber Kale; ; Monika Shah; ; Rutu Parekh
• Keywords: Sense amplifier; Access time

Heterogeneous 3D integration of single electron transistor (SET) circuits with CMOS based is achieved by stacking a SET layer above IC. Low power and delay efficient can be designed using SET. In this paper, we have simulated 6T SRAM array operating at room temperature comparable voltage. Peripheral circuit like sense amplifier, decoder, write pre-charge been for optimum performance. The stability cell verified N-curve method. 8 x bit 99.54 % efficient, 92.19 faster in access time 78.58 read compared to 16 nm SRAM. work voltage 800 mV, which scaled up 20 mV better efficiency. tested variation process, temperature. maximum frequency operation the memory controller 4 GHz.