A fully-mapped and energy-efficient FPGA accelerator for dual-function AI-based analysis of ECG

• DOI: 10.3389/fphys.2023.1079503
• Publication Date: 2023-02-06T06:52:17Z
• Authors: Wenhan Liu; Qianxi Guo; Siyun Chen; Sheng Chang; Hao Wang; Jin He; Qijun Huang
• Keywords: Hardware acceleration; Speedup; Gate array

In this paper, a fully-mapped field programmable gate array (FPGA) accelerator is proposed for artificial intelligence (AI)-based analysis of electrocardiogram (ECG). It consists 1-D convolutional neural network (CNN) and heart rate estimator, which constitute complementary dual-function analysis. The design projects each layer the CNN to hardware module on an Intel Cyclone V FPGA, virtual flatten effectively bridge feature extraction layers fully-connected layer. Also, maximizes computational parallelism accelerate inference. For it performs pipelined transformations, self-adaptive threshold calculation, heartbeat count without multiplexed usage resources. Furthermore, calculation elaborately analyzed optimized remove division acceleration, resulting in efficient method suitable implementation. According our experiments CNN, can achieve 43.08× 8.38× speedup compared with software implementations ARM-Cortex A53 quad-core processor Core i7-8700 CPU, respectively. are 25.48× 1.55× faster than two aforementioned platforms. Surprisingly, achieves energy efficiency 63.48 GOPS/W, obviously surpasses existing studies. Considering its power consumption only 67.74 mW, may be more resource-limited applications, such as wearable portable devices ECG monitoring.