A Universal-Verification-Methodology-Based Testbench for the Coverage-Driven Functional Verification of an Instruction Cache Controller

• DOI: 10.3390/electronics12183821
• Publication Date: 2023-09-11T13:09:21Z
• Authors: Cong Liu; Xinyu Xu; Zhenjiao Chen; Binghao Wang
• Keywords: Functional verification; Intelligent verification; Verilog; Runtime Verification; Software verification

The Cache plays an important role in computer architecture by reducing the access time of processor and improving its performance. hardware design is complex it challenging to verify functions, so traditional Verilog-based verification method no longer applicable. This paper proposes a comprehensive efficient testbench based on SystemVerilog language universal methodology (UVM) for instruction (I-Cache) controller. Corresponding testcases are designed each feature I-Cache controller automatically executed using python script electronic automation (EDA) tool. After simulating large number testcases, statistics reveal that module’s code coverage 99.13%. Additionally, both function assertion module reach 100%. Our results demonstrate these metrics meet requirements ensure thoroughness verification. Furthermore, established exhibits excellent scalability reusability, making easily applicable higher-level scenarios.