Energy and Precision Evaluation of a Systolic Array Accelerator Using a Quantization Approach for Edge Computing

• DOI: 10.3390/electronics13142822
• Publication Date: 2024-07-18T12:39:12Z
• Authors: Alejandra Sanchez...; Jordi Fornt; Lluc Alvarez; Bartomeu Alorda-L...
• Keywords: Systolic array; Edge device; Convolution (computer science)

This paper focuses on the implementation of a neural network accelerator optimized for speed and energy efficiency, use in embedded machine learning. Specifically, we explore power reduction at hardware level through systolic array low-precision data systems, including quantized approaches. We present comprehensive analysis comparing full precision (FP16) with (INT16) version an FPGA. upgraded FP16 modules to handle INT16 values, employing shifts enhance value density while maintaining accuracy. Through single convolution experiments, assess consumption error minimization. The paper’s structure includes detailed description accelerator, transition quantization, mathematical insights, instrumentation measurement, comparative error. Our results attempt identify pattern 16-bit quantization achieve significant savings minimal loss