RHBD Techniques to Mitigate SEU and SET in CMOS Frequency Synthesizers

• DOI: 10.3390/electronics8060690
• Publication Date: 2019-06-19T14:43:32Z
• Authors: V. Díez-Acereda; Sunil L. Khemchan...; J. del Pino; S. Mateos-Angulo
• Keywords: Radiation hardening; Single event upset; Upset

This paper presents a thorough study of radiation effects on frequency synthesizer designed in 0.18 μ m CMOS technology. In devices, the effect high energy particle impact can be modeled by current pulse connected to drain transistors. The SET (single event transient) and SEU upset) were analyzed connecting pulses drains all transistors analyzing amplitude variations phase shifts obtained at output nodes. Following this procedure, most sensitive circuits detected. proposes combination hardening-by-design techniques (RHBD) such as resistor–capacitor (RC) filtering or local circuit-redundancy mitigate radiation. proposed modifications make more robust against