Impacts of post-deposition annealing on hole trap generation at SiO2/p-type GaN MOS interfaces

• DOI: 10.35848/1882-0786/ad65b3
• Publication Date: 2024-07-20T00:12:31Z
• Authors: Kazuki Tomigahara; Masahiro Hara; Mikito Nozaki; Takuma Kobayashi; Heiji Watanabe
• Keywords: hole trap; MOSFETs; Physics; QC1-999; gallium nitride

Abstract In this study, impacts of post-deposition annealing (PDA) on hole trap generation at SiO2/p-GaN MOS interfaces are investigated. While the surface potential is strongly pinned due to severe hole trapping after 800 °C PDA, successful hole accumulation is observed when PDA is performed at 200 °C. The density of interface hole traps causing surface potential pinning, extracted from the hump in capacitance–voltage curves, is about 1012 cm–2 with 200 °C PDA, while over 1013 cm–2 when the PDA temperature exceeds 600 °C, regardless of the annealing ambient. Consequently, the origin of these hole traps is speculated to be defects generated by thermal effects.