JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores

• DOI: 10.48550/arxiv.1811.08091
• Publication Date: 2018-01-01
• Authors: Katie Lim; Jonathan Balkind; David Wentzlaff
• Keywords: FOS: Computer and information sciences; Hardware Architecture (cs.AR); Computer Science - Hardware Architecture; 7. Clean energy

Energy efficiency has become an increasingly important concern in computer architecture due to the end of Dennard scaling. Heterogeneity been explored as a way achieve better energy and heterogeneous microarchitecture chips have common mobile setting. Recent research using heterogeneous-ISA, microarchitecture, general-purpose cores further gains. However, there is no open-source hardware implementation heterogeneous-ISA processor available for research, effective on processors necessitates emulation speed provided by FPGA prototyping. This work describes our experiences creating JuxtaPiton integrating small RISC-V core into OpenPiton framework, which uses modified OpenSPARC T1 core. first time new integrated with open-source, general-purpose, processor. inherits all capabilities OpenPiton, including vital infrastructure can boot full-stack Debian Linux. Using this infrastructure, we investigate area timing effects performance running microbenchmarks.