Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning

• DOI: 10.48550/arxiv.2104.10712
• Publication Date: 2021-01-01
• Authors: Haowen Fang; Brady Taylor; Ziru Li; Zaidao Mei; Hai Li; Qinru Qiu
• Keywords: Neuromorphic engineering; Biological neuron model; Memristor; Limiting

Neuromorphic computing and spiking neural networks (SNN) mimic the behavior of biological systems have drawn interest for their potential to perform cognitive tasks with high energy efficiency. However, some factors such as temporal dynamics spike timings prove critical information processing but are often ignored by existing works, limiting performance applications neuromorphic computing. On one hand, due lack effective SNN training algorithms, it is difficult utilize dynamics. Many algorithms still treat neuron activation statistically. other utilizing also poses challenges hardware design. Synapses exhibit dynamics, serving memory units that hold historical information, simplified a connection weight. Most current models integrate synaptic activations in storage medium represent membrane institute hard reset after emits spike. This done its simplicity hardware, requiring only "clear" signal wipe medium, destroys stored neuron. In this work, we derive an efficient algorithm Leaky Integrate Fire neurons, which capable learn complex spatial patterns. We achieved competitive accuracy on two datasets. demonstrate advantage our model novel pattern association task. Codesigned algorithm, developed CMOS circuit implementation memristor-based network synapses retains reduced complexity. simulated ability react patterns adaptive threshold.