A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs

• DOI: 10.48550/arxiv.2207.11360
• Publication Date: 2022-10-03
• Authors: Fusco, Alexander; Hassan, Sahil; Mack, Joshua; Akoglu, Ali
• Keywords: Performance (cs.PF); FOS: Computer and information sciences; Computer Science - Performance; Hardware Architecture (cs.AR); 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology; Computer Science - Hardware Architecture

Non-uniform performance and power consumption across the processing elements (PEs) of heterogeneous SoCs increase the computation complexity of the task scheduling problem compared to homogeneous architectures. Latency of a software-based scheduler with the increased heterogeneity level in terms of number and types of PEs creates the necessity of deploying a scheduler as an overlay processor in hardware to be able to make scheduling decisions rapidly and enable deployment of real-life applications on heterogeneous SoCs. In this study we present the design trade-offs involved for implementing and deploying the runtime variant of the heterogeneous earliest finish time algorithm (HEFT_RT) on the FPGA. We conduct performance evaluations on a SoC configuration emulated over the Xilinx Zynq ZCU102 platform. In a runtime environment we demonstrate hardware-based HEFT_RT's ability to make scheduling decisions with 9.144 ns latency on average, process 26.7% more tasks per second compared to its software counterpart, and reduce the scheduling latency by up to a factor of 183x based on workloads composed of mixture of dynamically arriving real-life signal processing applications.<br/>Presented at 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (October 3-5)<br/>