68-Channel Highly-Integrated Neural Signal Processing PSoC with On-Chip Feature Extraction, Compression, and Hardware Accelerators for Neuroprosthetics in 22nm FDSOI

• DOI: 10.48550/arxiv.2407.09166
• Publication Date: 2024-07-12
• Authors: Liyuan Guo; Annika Weiße; Seyed Mohammad Al...; Franz Marcus Schü...; Marco Stolba; Qier Ma; Zhihai Zhuo; Stefan Scholze; Andreas Dixius; M. Berthel; Johannes Partzsch; Dennis Walter; Georg Ellguth; Sebastian Höppner; Richard George; Christian Mayr
• Keywords: PSoC; Neuroprosthetics; SIGNAL (programming language)

Multi-channel electrophysiology systems for recording of neuronal activity face significant data throughput limitations, hampering real-time, data-informed experiments. These limitations impact both experimental neurobiology research and next-generation neuroprosthetics. We present a novel solution that leverages the high integration density 22nm FDSOI CMOS technology to address these challenges. The proposed highly integrated programmable System-on-Chip comprises 68-channel 0.41 \textmu W/Ch frontends, spike detectors, 16-channel 0.87-4.39 action potential 8-channel 0.32 local field codecs, as well MAC-assisted power-efficient processor operating at 25 MHz (5.19 W/MHz). system supports on-chip training processes compression, inference neural sorting. sorting achieves an average accuracy 91.48% or 94.12% depending on utilized features. PSoC is optimized reduced area (9 mm2) power. On-chip processing compression capabilities free up bottlenecks in transmission (up 91% space saving ratio), moreover enable fully autonomous yet flexible processor-driven operation. Combined, design considerations overcome data-bottlenecks by allowing feature extraction subsequent compression.