Characterization and Mitigation of ADC Noise by Reference Tuning in RRAM-Based Compute-In-Memory

• DOI: 10.48550/arxiv.2502.05948
• Publication Date: 2025-02-09
• Authors: Wei Yan; Zishen Wan; Brian Crafton; Samuel Spetalnick; Arijit Raychowdhury
• Keywords: Characterization

With the escalating demand for power-efficient neural network architectures, non-volatile compute-in-memory designs have garnered significant attention. However, owing to nature of analog computation, susceptibility noise remains a critical concern. This study confronts this challenge by introducing detailed model that incorporates factors arising from both ADCs and RRAM devices. The experimental data is derived 40nm foundry test-chip, wherein different reference voltage configurations are applied, each tailored its respective module. mean standard deviation values HRS LRS cells through randomized vector, forming foundation simulation within our analytical framework. Additionally, examines read-disturb effects, shedding light on potential accuracy deterioration in networks due extended exposure high-voltage stress. phenomenon mitigated proposed low-voltage read mode. Leveraging comprehensive fault we evaluate CIM impact supervised learning (time-independent) reinforcement (time-dependent) tasks, demonstrate effectiveness tuning mitigate impacts.