FPGA-based Bit-Error-Rate Tester for SEU-hardened Optical Links

• DOI: 10.5170/cern-2009-006.636
• Publication Date: 2009-12-01
• Authors: S. Détraz; S Silva; P. Moreira; S Papadopoulos; Ioannis Papakonst...; S. Seif El Nasr; Christophe Sigaud; C. Soós; Pavel Stejskal; J. Troska; H Versmissen
• Keywords: Forward error correction; Virtex

The next generation of optical links for future High-Energy Physics experiments will require components qualified use in radiation-hard environments. To cope with radiation induced single-event upsets, the physical layer protocol include Forward Error Correction (FEC). Bit-Error-Rate (BER) testing is a widely used method to characterize digital transmission systems. In order measure BER and without proposed FEC, simultaneously on several devices, multi-channel tester has been developed. This paper describes architecture tester, its implementation Xilinx Virtex-5 FPGA device discusses experimental results.