A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS

• DOI: 10.5555/2016802.2016869
• Publication Date: 2011-08-01
• Authors: Ming‐Hung Chang; Yi-Te Chiu; Shu-Lin Lai; Wei Hwang
• Keywords: Interleaving; Subthreshold conduction; Low-power electronics

Subthreshold SRAM is a significant approach to reduce power consumption in energy-constrained SoC design. For the ultra-low consideration, primary concerns of are stability and reliability instead performance. In this paper, proposed 9T bit-cell enhances write ability by cutting off positive feedback loop inverter pair. read mode, isolated path storage node enlarge SNM. Besides, subthreshold enable implementation bit-interleaving structure which achieves soft-error tolerance. The able operate at voltage as low 0.3V. One extra virtual ground (VVSS) line used bit-line leakage ensure data can be successfully. A 1kb bit-interleaved implemented UMC 65nm 1P10M CMOS technology verify scheme, operates minimum energy point (0.3V) with 5.824pJ for one operation.