an analytical memory hierarchy model for performance prediction

• DOI: 10.5555/3242181.3242251
• Publication Date: 2017-12-01
• Authors: Sunil Thulasidasan; Stephan Eidenbenz; Gopinath Chennupati; Nandakishore Santhi
• Keywords: 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology

As the US Department of Energy (DOE) invests in exascale computing, performance modeling of physics codes on CPUs remain a challenge in computational co-design due to the complex design of processors that include memory hierarchies, instruction pipelining, and speculative execution. We present Analytical Memory Model (AMM), a model of cache memory hierarchy, embedded in the Performance Prediction Toolkit (PPT) — a suite of discrete-event-simulation-based codesign hardware and software models. AMM enables PPT to significantly improve the quality of its runtime predictions of scientific codes. At its technical core, AMM uses a computationally efficient, stochastic method to predict the distributions of reuse distances of a scientific code, where reuse distance is a hardware architecture-independent measure of the patterns of virtual memory accesses. AMM relies on a stochastic, static basic block-level analysis of reuse distance distributions measured from the memory traces of the scientific applications on small instances. The analytical reuse distribution is useful to estimate the effective latency and throughput of a memory access, which in turn are used to predict the overall runtime of a scientific application. The experimental results show that the predicted and actual runtimes of two scientific mini-applications (matrix multiplication and Blackscholes) are similar, while AMM is a scalable approach.