instruction scheduling for power reduction in processor based system design

• DOI: 10.5555/368058.368439
• Publication Date: 2002-11-27
• Authors: Akihiko Inoue; Hiroto Yasuura; Tohru Ishihara; Hiroyuki Tomiyama
• Keywords: 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology

This paper proposes an instruction scheduling technique to reduce power consumed for off-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and a scheduling algorithm is also presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithm.