A Non-binary C-R Hybrid DAC for 12 b 100 MS/s CMOS SAR ADCs with Fast Residue Settling

• DOI: 10.5573/jsts.2021.21.4.255
• Publication Date: 2021-09-23T00:41:58Z
• Authors: Jae-Geun Lim; Seung-Hoon Lee; Je-Min Jeon; Jun-Ho Boo; Yoon-Bin Im; Jae-Hyuk Lee; Sung-Han Do; Young-Jae Cho; Michael Choi; Gil-Cho Ahn
• Keywords: Spurious-free dynamic range; Successive approximation ADC; Settling time

This work proposes two versions of a 12 b 100 MS/s successive-approximation register (SAR) ADC based on non-binary C-R hybrid DAC. The proposed DAC applies weighted capacitor array to the 7 MSBs meet settling requirement output and determines remaining 5 LSBs using reference voltages generated from simple resistor string reduce area significantly. Version 1 in 28 ㎚ CMOS adopts synchronous SAR logic comparator with tail reset switch minimize power consumption. 2 0.18 ㎛ employs an asynchronous meta-stability correction achieve high-speed operation. which has active die 0.042 ㎟ shows maximum signal-to-noise-and-distortion ratio (SNDR) spurious-free dynamic range (SFDR) 62.3 77.3 ㏈, respectively, consuming 1.3 ㎽ 1.0 V supply voltage. is similar analog circuit topology, showing SNDR SFDR 60.1 73.5 0.30 ㎟, operating at 1.8